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| SMH4804 -48V Programmable Hot Swap Sequencing Power Controller - - FEATURES AND APPLICATIONS INTRODUCTION The SMH4804 is a user-programmable -48V power supply controller designed to control the hot-swapping of plug-in cards and to sequence supplies in a distributed power environment. The SMH4804 drives an external power MOSFET switch that connects the bus side supply to the card side load and controls in-rush current while providing both current regulation and over-current protection. When the source and drain voltages of the external MOSFET are within specification, the SMH4804 asserts four PG[4:1]# power-good logic outputs either simultaneously or sequenced at programmable intervals to enable DC-DC converters to distribute card side power. Additional features of the device include: UV and OV monitor, master enable or temperature sense input (EN/ TS), 2.5V and 5V reference outputs for expanding monitor functions, two Pin-Detect enable inputs (PD1# and PD2#) for card insertion verification, and duty-cycle or latched over-current protection modes. All features are programmed in nonvolatile registers through the I2C interface which is simplified with the SMX3200 interface adapter and Windows GUI software available from Summit Microelectronics. Engineers can program the device directly in-circuit with units of voltage, current and time, allowing fast design cycles. Features: * Soft Starts Main Power Supply on Card Insertion or System Power Up * In-Rush Current Limiting * Master Enable to Allow System Control of Power Up or Down * Programmable Independent Control of up to 4 DC/DC Converters via 4 Power Good Signals, PG[4:1]# * Highly Programmable Circuit Breaker Level and Mode - Programmable Quick-TripTM Value, Current Limiting, Duty Cycle Times, and Over-Current Filter * Programmable Host Voltage Fault Monitoring - Programmable UV/OV Filter and UV Hysteresis * Programmable Fault Mode: Latched or Duty Cycle * Internal Shunt Regulator Allows for a Wide Supply Range (typically -32 to -72 Volts) * I2C 2-Wire Serial Bus Interface for Programming, Power On/Off and Operational Status Applications: * Telecom Hot-Swap Card * Distributed Power Architectures * Power-on LAN, IEEE 802.3 - SIMPLIFIED APPLICATION DRAWING 9 571 9 ' 'XDO 00%' 9 6KRUW 3LQV 9 ' 9 ' 5 . 5 . 966 5 . 29 5' . : 5 5 9'' 3' 3' 95() 95() )6 $ $ $ 6'$ 6&/ 9LQ 9RXW 2Q2II 9RXW 9LQ 9 , & 3* 60+ 89 'UDLQ6HQVH &%6HQVH 3* 3* 9LQ 9RXW 2Q2II 9RXW 9LQ 9 9*DWH 3* 1RWH 9LQ 9RXW 2Q2II 9RXW 9LQ 9 & Q) 5 5 . 5 . & Q) ' 00%' ' 9 ' 9 & Q) 5 & Q) 9LQ 9RXW 2Q2II 9LQ 9RXW 9 4 ,5)1 1RWH 6DIHW\ LVRODWLRQ LQWHUIDFH PD\ EH UHTXLUHG 6HH $SSV 6HFWLRQ Figure 1. SMH4804 Simplified Application Diagram (c) SUMMIT Microelectronics, Inc. 2002 * 300 Orchard City Drive #131 * Campbell CA 95006 * Phone 408 378-6461 * Fax 408 378-6596 * www.summitmicro.com 2050 3.7 10/30/02 1 Functional Block Diagram - SMH4804 FUNCTIONAL BLOCK DIAGRAM SCL 11 SDA 10 2.5VREF 20 ENPGA ENPGB ENPGC 23 22 21 50k 27 PG4# 50k 12VREF 28 50k VDD PROGRAMMING STEERING LOGIC 50k 50k PROGRAMMABLE DELAY 24 PG3# 50k 200k 50k 10A + - + - + PROG REF - + P. D. FILTER PROGRAMMABLE DELAY 25 EN/TS PD1# PD2# 4 PROGRAMMABLE DELAY 26 PG2# 5 6 UV 15 PG1# 17 1 DRAIN SENSE 5V 12V 2.5V VSS A0 A1 A2 MODE RESET# 14 2 13 16 9 8 PROGRAMMABLE DELAY 50mV CBSENSE 12 Programmable Quick Response Ref. Voltage 2 - Three @ 50k 50k 50k DEVICE ADDRESS DECODE P. D. FILTER + - + - OV OV/UV FILTER 19 5.0VREF VGATE SENSE 3 VGATE FAULT LATCH AND DUTY CYCLE TIMER 7 FAULT# Programmable Shutdown Timer 18 FS# 2050 BD Figure 2. SMH4804 Block Diagram 2050 3.7 10/30/02 Summit Microelectronics SMH4804 -\ Functional Description FUNCTIONAL DESCRIPTION The SMH4804 integrated hot swap power controller operates within a wide supply range, typically -32 to -72 volts, and generates the signals necessary to drive isolatedoutput DC/DC converters. The general start-up procedure is as follows: * A physical connection must first be made with the chassis to discharge any electrostatic voltage potentials when a typical add-in board is inserted into the powered backplane. * The board then contacts the long pins on the backplane that provide power and ground. * As soon as power is applied the device starts up, but does not immediately apply power to the output load. * Under-voltage and over-voltage circuits inside the controller verify that the input voltage is within a userspecified range. * The SMH4804 senses the PD1# and PD2# pin detection signals to indicate the card is seated properly. These requirements must be met for a Pin Detect Delay period of tPDD. Once this time has elapsed, the hot-swap controller enables VGATE to turn on the external power MOSFET switch. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the drain sense input. When DRAIN SENSE drops below 2.5V, and VGATE rises above VDD - VGT, the SMH4804 asserts the PG1# through PG4# power good outputs to enable the DC/ DC controllers. The ENPGA, ENPGB, and ENPGC Power Good Enable inputs may be used to activate or deactivate specific output loads. Steady-state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controllers by shutting down the power MOSFET: * an under-voltage or over-voltage condition on the host power supply. * an over-current event detected on the CBSENSE input * a failure of the power MOSFET sensed via the DRAIN SENSE pin. * the PD1#/PD2# pin detect signals becoming invalid. * the master enable (EN/TS) falls below 2.5V. * the FS# input is driven low by events on the secondary side of the DC/DC controllers. The SMH4804 may be configured so that after any of these events occurs, the VGATE output shuts off and either latches into an off state, or recycles power after a cooling down period, tCYC. Summit Microelectronics Powering VDD The SMH4804 contains an internal shunt regulator on the VDD pin that prevents the voltage from exceeding 12V. It is necessary to use a dropper resistor (RD) between the host power supply and the VDD pin in order to limit current into the device and prevent possible damage. The dropper resistor allows the device to operate across a wide range of system supply voltages, typically -32 V to -72V, and also helps protect the device against common-mode power surges. Refer to the Applications Section for help on calculating the RD resistance value. Hot-Swap Verification There are several enabling inputs that allow the host to control the SMH4804. The Pin Detect signals (PD1# and PD2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. These inputs must be held low for a pin-detect delay period of tPDD before a power-up sequence may be initiated. This is typically done by clamping the inputs to VSS through the implementation of an ejector switch, or alternatively through the use of staggered pins at the card-cage interface. The pin detect delay (tPDD) timing parameter is controlled by bits 1:0 of register 9. Refer to Register 9 - Address 1001 on page 38 for more information. Two shorter pins, arranged at opposite ends of the connector, force the card to be fully seated before both pin detects are enabled. Care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. Refer to details in the Applications Section for proper circuit implementation. Note that the PD1# and PD2# inputs are enabled or disabled using bit 0 of Register 3. Refer to Register 3 - Address 0011 on page 32 for more information. The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. This input signal must exceed 2.5V (nominal) for proper operation. Refer to the Pin Descriptions on page 10 for more information. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense whether or not the host supply voltage is within the user-defined limits. The power-up sequence is initiated when the input to the UV pin rises above 2.5V and the input to the OV pin falls below 2050 3.7 10/30/02 3 Functional Description 2.5V for a period of at least tPDD (Pin Detect Delay time). The tPDD filter helps prevent spurious start-up sequences while the card is being inserted. If UV falls below 2.5V or OV rises above 2.5V, the PG[4:1]# and VGATE outputs are disabled immediately. SMH4804 The falling voltage compare level may be set in steps of 62.5mV below 2.5V. The rising voltage compare level is fixed at 2.5V. The default under-voltage hysteresis level is set to 62.5mV. In default conditions the SMH4804 is not in an under-voltage state once the UV voltage rises above 2.5V; and after that an under-voltage occurrence is not recognized until the UV voltage falls below 2.4375V (2.5V - 62.5mV). Under-/Over-Voltage Filtering The SMH4804 can be configured so that an out-oftolerance condition on UV/OV does not shut off the output immediately. Instead, a filter delay may be inserted so that only sustained under-voltage or over-voltage conditions can shut off the output. An out-of-tolerance condition on UV/OV for longer than the filter delay time (tUOFLTR in Figure 3) causes the VGATE and PG[4:1]# outputs to shut off when the UV/OV filter option is enabled using bits 2:1 of Register 4. The under-/over-voltage filtering feature is disabled (bits 2:1 = 00) in the default configuration. Refer to Register 4 Address 0100 on page 33 for more information on the filter delay options. The UV and OV filters are enabled and disabled by programming bits 3 and 2 of Register 6 respectively. Refer to Register 6 - Address 0110 on page 36 for more information. Note that the delay values in Register 4 are only valid if the corresponding over or under voltage filtering is enabled using bits 3:2 of Register 6. Figure 3 shows the timing for the under-/over-voltage filter. Soft Start Slew Rate Control Once all of the preconditions for powering up the DC/DC controllers have been met as explained in the previous sections, the SMH4804 provides a means to soft start the external power MOSFET. It is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. For example, charging the filter capacitance too quickly (normally required at the input of the DC/DC controllers) may generate very high current. The VGATE output of the SMH4804 is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. The slew rate may be found by dividing IVGATE by the gate-to-drain capacitance placed on the external FET. Load Control -- Sequencing the Secondary Supplies The PG1# through PG4# output pins are used to enable the external DC/DC controllers. Once the card is inserted, the SMH4804 samples the PD1# and PD2# pin detect input pins to determine if the card as been inserted properly. It then monitors the state of the UV and OV input pins to assure there is no under-voltage or over-voltage condition present. Once these conditions are met, and the EN/TS pin is greater than 2.5V, the SMH4804 asserts the VGATE output to turn on the external MOSFET. During the time it takes to turn the MOSFET on, the SMH4804 monitors the system for an over-current condition via the CBSENSE input pin. In addition, the device internally monitors the voltage level on the VGATE output pin. This is shown by the `VGATE Sense' block in Figure 2. Once power has been ramped to the DC/DC controllers, two conditions must be met before the PG[4:1]# outputs can be enabled: * the DRAIN SENSE input voltage must be below 2.5V. * the VGATE voltage must be greater than VDD - VGT, where VGT is the gate threshold. The DRAIN SENSE input helps ensure that the power MOSFET is not absorbing too much steady state power from operating at a high VDS. This sensor remains active at all times (except when current regulation is enabled). The Summit Microelectronics 2.5V OV / UV tUOFLTR FAULT# 2050 Fig07 Figure 3. Under-/Over-Voltage Filter Timing Under-/Over-Voltage Latching An additional option for an out-of-tolerance condition on UV/ OV is to latch the VGATE and PG[4:1]# outputs off such that a return to normal UV/OV operation does not turn them back on. In this case the FAULT# output is asserted. Under-Voltage Hysteresis The Under-Voltage comparator input may be configured with a programmable level of hysteresis using Register 7. 4 2050 3.7 10/30/02 SMH4804 VGATE sensor makes sure that the power MOSFET is operating well into its saturation region before allowing the loads to be switched on. Once VGATE reaches VDD - VGT this sensor is latched. PG1# Functional Description tPGD When the external MOSFET is properly switched on the PG[4:1]# outputs may be enabled. Output PG1# is activated first, followed by PG2# after a delay of tPGD, PG3# after another tPGD delay, and PG4# after a final tPGD delay. The delays built into the SMH4804 allow timed sequencing of power to the loads. The delay times are programmable from 50s to 160ms using bits 3:2 of Register 3 and bit 3 of Register 9. Refer to Register 3 - Address 0011 on page 32 and Register 9 - Address 1001 on page 38 for more information. The ENPGA, ENPGB, and ENPGC input pins in Figure 5 are used to enabled the PG[4:1]# outputs. The ENPGA pin controls the PG[4:2]# outputs. If ENPGA is deasserted by external logic, the SMH4804 disables the PG[4:2]# outputs and they enter the high-impedance state. The ENPGA input must be asserted in order for PG[4:2]# to be driven by the SMH4804. The ENPGB pin controls the PG[4:3]# outputs. If ENPGB is deasserted by external logic, the SMH4804 disables the PG[4:3]# outputs and they enter the high-impedance state. The ENPGB input must be asserted in order for PG[4:3]# to be driven by the SMH4804. The ENPGC pin controls the PG[4]# output. If ENPGC is deasserted by external logic, the SMH4804 disables the PG[4]# outputs and the output enters the high-impedance state. The ENPGC input must be asserted in order for PG[4]# to be driven by the SMH4804. This cascaded control mechanism is useful for enabling supplies that have dependencies based on the other voltages in the system. The PG[4:1] outputs have a 12V withstand capability, so high voltages must not be connected to these pins. Bipolar transistors or opto-isolators can be used to boost the withstand voltage to that of the host supply. Refer to Figure 18 for connectivity information. Figure 5 shows the relationship between the PG[4:1]# and the ENPG[C:A] signals. ENPGA tPGD PG2# ENPGB tPGD PG3# ENPGC PG4# 2050 Fig02 2.1 Figure 4. PG Output and ENPG Input Relationship Forced Shutdown -- Secondary Feedback The Forced Shutdown signal (FS#) is an active low input that provides a method of receiving feedback from the secondary side of the DC/DC controllers. A built-in shutdown timer allows the SMH4804 to ignore the state of the FS# input until the timer period expires. The timer period is defined in bits 2:0 of Register 5. The FS# input must be driven high by the end of this timer period. A low level on this input causes a Fault condition, driving the FAULT# pin low and shutting off the VGATE and PG[4:1]# outputs. The purpose of the shutdown timer is to allow enough time for devices on the secondary side of the DC/DC controllers to power up and stabilize. This feature allows supervisory circuits such as an SMS44 to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. Alternatively, the FS# input can be programmed to act as a fourth ENPG input controlling the PG1# output. This is combined with an option to independently enable PG1# with no affect on the other PG[4:2]# outputs, or it can be programmed so PG1# is the enabling output for the other outputs. Summit Microelectronics 2050 3.7 10/30/02 5 Functional Description Circuit Breaker Operation The SMH4804 provides a number of circuit breaker functions to protect against over-current conditions. A sustained over-current event could damage the host supply and/or the load circuitry. The board's load current passes through a series resistor (RS) connected between the MOSFET source (which is tied to CBSENSE) and VSS. The breaker trips whenever the voltage drop across RS is greater than 50mV for more than tCBD (a programmable filter delay ranging from 10s to 500s). The circuit breaker cycle time is controlled via bit 0 of Register 4. RESET# TCBD CBSENSE SMH4804 50mV TPDD VGATE TCBRST Figure 5 shows the circuit breaker duty cycle operation with RESET# high. 2050 Fig04 2.1 Figure 6. Circuit Breaker Reset with RESET# Low Quick-TripTM Circuit Breaker TCBD CBSENSE 50mV TCBD TCYC VGATE The SMH4804 provides a Quick-TripTM feature that causes the circuit breaker to trip immediately if the voltage drop across 56 exceeds VQCB. The Quick-Trip level may be set to 60mV, 100mV (default), 200mV, or the feature may be disabled. Refer to bits 1:0 of Register 2 - Address 0010 on page 31 for more information. Figure 7 shows the circuit breaker `Quick Trip' response.In this figure, the voltage rises above VQCB, causing VGATE to be deasserted. 2050 Fig03 1.0 Figure 5. Circuit Breaker Duty Cycle Operation with RESET# High Figure 6 shows the behavior of VGATE and CBSENSE immediately after RESET# is deasserted. The circuit breaker cycle time can be programmed to a value of either 2.5 seconds of 5 seconds depending on the system configuration. Refer to bit 0 of Register 4 - Address 0100 on page 33 for more information on selecting the circuit breaker cycle time. CBSENSE TFSTSHTDN VGATE 2050 Fig05 2.0 Figure 7. Circuit Breaker Quick Trip Response Current Regulation The current regulation mode is an optional feature that provides a means to regulate current through the MOSFET for a programmable period of time using bits 1:0 of Register 6. 6 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Current regulation is generally enabled in applications that have switched dual (A and B) distributed power sources. By using the current regulation function, unwarranted shutdowns can be avoided if one of the dual supplies is switched in when it is at a more negative potential the currently operating supply. When current regulation is selected by programming bits 1:0 of Register 6 to a binary value of 01 (5 ms), 10 (80 ms), or 11 (160 ms), it is enabled during a soft-start (power on period) and during normal operation after the PG[4:1]# outputs are enabled. If the voltage monitored at the CBSENSE pin is greater than 50mV, but less than 60mV, the SMH4804 reduces the VGATE voltage in order to maintain a CBSENSE potential less than 60mV, effectively regulating the current through the MOSFET. Figure 8 and Figure 9 illustrate the current regulation function. The time period tPCR -- selectable at 5, 80, or 160 ms -- is the maximum time during which regulation is enforced. If either VQCB or tPCR are exceeded the VGATE and PG[4:1]# outputs are immediately deasserted. However, if CBSENSE drops below 50mV before the timer period ends, the timer is reset and VGATE resumes normal operation (see Current Regulation With Recovery on page 7). If the Quick-Trip level is exceeded, the device bypasses the current regulation timer and shuts down immediately. The current regulation feature is disabled in the default configuration. Functional Description VQCB CBSENSE tPCR 50mV 0V 12V VGATE 0V 2050 Fig06b Figure 9. Current Regulation Without Recovery Nonvolatile Fault Latch The SMH4804 provides an optional nonvolatile fault latch (NVFL) circuit breaker feature. The nonvolatile fault latch essentially provides a programmable fuse on the circuit breaker. When the latch is enabled by setting bit 5 of Register 5, the nonvolatile fault latch is set whenever the circuit breaker trips. Once set, it cannot be reset by cycling power or through the use of the RESET# pin. Note: The device remains disabled until Register C is reprogrammed. Refer to Register C - Address 1100 on page 38 for more information. As long as the NVFL is set, the FAULT# output remains asserted. The Nonvolatile Fault Latch feature is disabled in the default configuration. VQCB CBSENSE Resetting FAULT# When the circuit breaker trips, the VGATE output is turned off and the SMH4804 drives FAULT# low. There are two methods to reset the circuit breaker which are selectable with the MODE pin: * When the MODE is held high or left floating, the circuit breaker is in the duty-cycle mode. In this case the breaker resets automatically after a time of tCYC. * When the MODE pin is held low (or disabled in the Configuration Register) FAULT# can be reset by bringing RESET# low. The VGATE output attempts to restart the MOSFET slew control circuitry tPDD after bringing RESET# back high again. In either case, cycling power to the board resets the circuit breaker. If the over current condition still exists after the MOSFET switches back on, the circuit breaker will re-trip. 0V 2050 Fig06a Figure 8. Current Regulation With Recovery Summit Microelectronics 2050 3.7 10/30/02 7 Functional Description Serial Interface The SMT4804 uses the industry standard I2C, 2-wire serial data interface. This interface provides access to the configuration registers and the nonvolatile fault latch. The interface has three address inputs (A0 - A2) allowing up to eight devices on the same bus. This allows multiple devices on the same board or multiple boards in a system to be controlled with two signals; SDA and SCL. Device configuration utilizing the Windows based SMT4804 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMT4804. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. SMH4804 8 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - Package And Pin Configurations PACKAGE AND PIN CONFIGURATIONS PACKAGE AND PIN CONFIGURATIONS 28-Pin SOIC DRAIN SENSE A0 VGATE EN/TS PD1# PD2# FAULT# RESET# MODE SDA SCL CBSENSE A1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD PG4# PG2# PG1# PG3# ENPGA ENPGB ENPGC 2.5VREF 5VREF FS# OV A2 UV 2050 SOIC PCon 2.1 Figure 10. 28-Pin SOIC Package Pinout 48-Pin TQFP DRAIN SENSE VGATE PG4# 48 47 46 45 44 43 42 41 40 39 38 37 PG2# VDD A0 EN/TS PD1# PD2# FAULT# RESET# MODE SDA SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 PG1# PG3# ENPGA ENPGB ENPGC 2.5VREF 5VREF FS# CBSENSE A1 VSS VSS UV A2 2050 TQFP PCon 2.1 Figure 11. 48-Pin TQFP Package Pinout1 $OO FRQQHFWV Summit Microelectronics XQQDPHG SLQV RQ WKLV OV SDFNDJH DUH QR 2050 3.7 10/30/02 9 Pin Descriptions - SMH4804 PIN DESCRIPTIONS Table 1 provides the type, name, and description of the SMH4804 pins. Pin numbers are provided for both the 28-pin SOIC and 48-pin TQFP packages. Pin Number (28-Pin SOIC) Pin Number (48-Pin TQFP) Pin Type (I/O) Pin Name Description 1 44 I DRAIN SENSE The DRAIN SENSE input monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. An internal 10A source pulls the DRAIN SENSE signal towards the 5V reference level. DRAIN SENSE must be held below 2.5V to enable the PG[4:1] outputs. The A0 input works in conjunction with the A1 and A2 inputs. Together these inputs are used for decoding multiple devices on the serial bus. The A0 input has an internal 50K pull-up to 5V. The VGATE output activates an external power MOSFET switch. This signal supplies a constant current output (100A typical), which allows easy adjustment of the MOSFET to turn on slew rate. The Enable/Temperature Sense input is the master enable input. If EN/TS is less than 2.5V, VGATE is disabled. This pin has an internal 200K pull-up to 5V. The PD1# pin works in conjunction with the PD2# pin to optionally enable VGATE and the PG[4:1]outputs when they are at VSS. This pin has an internal 50K pull-up to 5V. The PD2# pin works in conjunction with the PD1# pin to optionally enable VGATE and the PG[4:1]# outputs when they are at VSS. This pin has an internal 50K pull-up to 5V. FAULT# is an open-drain, active-low output that indicates the fault status of the device. The RESET# pin is used to clear latched fault conditions. When this pin is asserted, the VGATE and PG[4:1]# outputs are disabled. Refer to the section on Circuit Breaker Operation for more information. This pin has an internal 50K pull-up to 5V. SDA is the bidirectional serial data I/O port. This pin has an internal 50K pull-up to 5V. 2 46 I A0 3 48 O VGATE 4 1 I EN/TS 5 2 I PD1# 6 3 I PD2# 7 8 5 7 O I FAULT# RESET# 9 9 I/O SDA Table 1. SMH4804 Pin Descriptions 10 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Pin Number (28-Pin SOIC) Pin Number (48-Pin TQFP) Pin Type (I/O) Pin Name Pin Descriptions Description 10 10 I MODE The state of the MODE signal determines how fault conditions are cleared. The device is in latched mode when this pin is low, and in cycle mode when the pin is high or floating. SCL is the serial clock input. This pin has an internal 50K pull-up to 5V. The circuit breaker sense input is used to detect overcurrent conditions across an external, low value sense resistor (RS) tied in series with the Power MOSFET. A voltage drop of greater than 50mV across the resistor for longer than tCBD trips the circuit breaker. A programmable Quick-TripTM sense point is also available. The A1 input works in conjunction with the A0 and A2 inputs. Together these inputs are used for decoding multiple devices on the serial bus. The A1 input has an internal 50K pull-up to 5V. This is connected to the negative side of the supply. The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE is disabled if UV is less than 2.5V. Programmable internal hysteresis is available on the UV input, adjustable in increments of 62.5mV. Also available is a filter delay on the UV input. The A2 input works in conjunction with the A0 and A1 inputs. Together these inputs are used for decoding multiple devices on the serial bus. The A2 input has an internal 50K pull-up to 5V. The OV pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE is disabled if OV is greater than 2.5V. A filter delay is available on the OV input. The Forced Shutdown (FS#) pin is an active low input that causes VGATE and the PG[4:1]# outputs to be shut down at any time after an internal shutdown timer has expired. The shutdown timer allows supervisory circuits on the secondary side (which are not powered up initially) to control shut down of the SMH4804 via an opto-isolator. This input has no pull-up resistor. This is a precision 5V output reference voltage that may be used to expand the logic input functions on the SMH4804. The output reference voltage is with respect to VSS. 11 12 12 13 I I SCL CBSENSE 13 15 I A1 14 15 17 20 I I VSS UV 16 22 I A2 17 24 I OV 18 25 I FS# 19 26 O 5VREF Table 1. SMH4804 Pin Descriptions (Continued) Summit Microelectronics 2050 3.7 10/30/02 11 Pin Descriptions Pin Number (28-Pin SOIC) Pin Number (48-Pin TQFP) Pin Type (I/O) Pin Name Description SMH4804 20 28 O 2.5VREF This is a precision 2.5V output reference voltage that may be used to expand the logic input functions on the SMH4804. The output reference voltage is with respect to VSS. The active-high ENPGC input controls the PG4# output. When ENPGC is low, the PG4# output is immediately placed in a high-impedance state. When ENPGC is high, or left floating, PG4# is driven low at a time period of tPGD after PG3# is asserted. This pin has an internal 50k pull-up to 5V. The active-high ENPGB input controls the PG3# and PG4# outputs. When ENPGB is low, the PG3#, and PG4# outputs are immediately placed in a highimpedance state. When ENPGB is high, or left floating, PG3# is driven low at a time period of tPGD after PG2# is asserted. This pin has an internal 50k pull-up to 5V. The active-high ENPGA input controls the PG2#, PG3#, and PG4# outputs. When ENPGA is low, the PG2#, PG3#, and PG4# outputs are immediately placed in a high-impedance state. When ENPGA is high, or left floating, PG2# is driven low at a time period of tPGD after PG1# is asserted. This pin has an internal 50k pull-up to 5V. The PG3# output is an open-drain, active low signal with no internal pull-up resistor. This pin can be used to switch a load or enable a DC/DC converter. PG1# is enabled immediately after VGATE reaches VDD VGT and the DRAIN SENSE voltage is less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) is enabled tPGD after its predecessor, provided that the ENPGx inputs are high. The voltage on this pin cannot exceed 12V relative to VSS. ENPGx refers to the ENPGA, ENPGB, and ENPGC inputs. The PG1# output is an open-drain, active low signal with no internal pull-up resistor. This pin can be used to switch a load or enable a DC/DC converter. PG1# is enabled immediately after VGATE reaches VDD VGT and the DRAIN SENSE voltage is less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) is enabled tPGD after its predecessor, provided that the ENPGx inputs are high. The voltage on this pin cannot exceed 12V relative to VSS. ENPGx refers to the ENPGA, ENPGB, and ENPGC inputs. 21 29 I ENPGC 22 30 I ENPGB 23 32 I ENPGA 24 34 O PG3# 25 36 O PG1# Table 1. SMH4804 Pin Descriptions (Continued) 12 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Pin Number (28-Pin SOIC) Pin Number (48-Pin TQFP) Pin Type (I/O) Pin Name Pin Descriptions Description 26 37 O PG2# The PG2# output is an open-drain, active low signal with no internal pull-up resistor. This pin can be used to switch a load or enable a DC/DC converter. PG1# is enabled immediately after VGATE reaches VDD VGT and the DRAIN SENSE voltage is less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) is enabled tPGD after its predecessor, provided that the ENPGx inputs are high. The voltage on this pin cannot exceed 12V relative to VSS. ENPGx refers to the ENPGA, ENPGB, and ENPGC inputs. The PG4# output is an open-drain, active low signal with no internal pull-up resistor. This pin can be used to switch a load or enable a DC/DC converter. PG1# is enabled immediately after VGATE reaches VDD VGT and the DRAIN SENSE voltage is less than 2.5V. Each successive PGn# output (PG2# PG3# PG4#) is enabled tPGD after its predecessor, provided that the ENPGx inputs are high. The voltage on this pin cannot exceed 12V relative to VSS. ENPGx refers to the ENPGA, ENPGB, and ENPGC inputs. This is the positive supply input. An internal shunt regulator limits the voltage on this pin to approximately 12V with respect to VSS. A resistor must be placed in series with the VDD pin to limit the regulator current (RD in the application illustrations). 27 40 O PG4# 28 42 I VDD Table 1. SMH4804 Pin Descriptions (Continued) Summit Microelectronics 2050 3.7 10/30/02 13 Absolute Maximum Ratings - - SMH4804 RECOMMENDED OPERATING CONDITIONS Temperature Range (Ambient) ................. -40o C to +85o C Supply Voltage(VDD) (IDD = 5 mA)..................... 11V to 13V Package Thermal Resistance (JA) 28-pin SOIC ... 79oC/W Package Thermal Resistance (JA) 48-pin TQFP... 80oC/W Moisture Classification Level 3 (MSL 3) per J-STD-020 Reliability Characteristics Data Retention..................................................... 100 Years Endurance1 ................................................. 100,000 Cycles ABSOLUTE MAXIMUM RATINGS Temperature Under Bias............................. -55C to 125C Power Supply Current (IDD) .......................................15 mA Storage Temperature .................................. -65C to 150C Lead Solder Temperature (10 seconds) ................... 300 C Terminal Voltage with Respect to VSS: VGATE ...................................................... VDD + 0.3V A0, A1, A2, MODE, RESET, ENPGA, ENPGB, ENPGC, FS#, SDA, and SCL..................... -0.3 to +7V PD1#, PD2#, VDD, UV, OV, CBSENSE, DRAIN SENSE, EN/TS, FAULT#, PG1#, PG2#, PG3#, and PG4# ................................................. -0.3 to +15V Open Drain Output Short Circuit Current.................100 mA Junction Temperature ...............................................150o C ESD Rating per JEDEC .............................................2000V Latch-Up testing per JEDEC.................................. 100mA Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. *XDUDQWHHG E\ 'HVLJQ 14 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - DC Operating Characteristics DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit VDD 5VREF ILOAD5 2.5VREF ILOAD2.5 IDD1 VUV VUVHYST VOV VOVHYST VGATE IGATE VSENSE ISENSE VCB VQCB Supply voltage 5V reference output voltage 5V reference output current 2.5V reference output voltage 2.5V reference output current Power supply current Under-voltage threshold Under-voltage hysteresis Over-voltage threshold Over-voltage hysteresis VGATE output voltage VGATE output current DRAIN SENSE threshold DRAIN SENSE current output Circuit breaker threshold Programmable Quick Trip circuit breaker threshold voltage IDD = 3 mA IDD = 3 mA IDD = 3 mA IDD = 3 mA IDD = 3 mA 11 4.8 -1 2.45 -0.5 2 12 5.00 13 5.25 1 V V mA V mA mA V mV 2.50 2.55 0.5 13 IDD = 3 mA IDD = 3 mA IDD = 3 mA IDD = 3 mA IGATE = 80 A VGATE = 5 V VSENSE = VSS IDD = 3 mA IDD = 3 mA QT = 200 mV QT = 100 mV QT = 60 mV 2.45 2.50 632 2.55 2.45 2.50 10 2.55 V mV VDD - VGT 80 2.45 9 45 180 90 54 2.40 85 2.50 10 50 200 100 60 2.45 10 3 -0.1 VDD 90 2.55 11 55 220 110 66 2.50 V A V A mV mV mV mV V mV VENTS VENTSHYST VIH VIL VOL EN/TS threshold voltage EN/TS threshold hysteresis voltage Input voltages: ENPGA/B/C, MODE, RESET#, PD1#, PD2# Output low voltage: FAULT# Output low voltage: PG1#/2#/3#/ 4# IDD = 3 mA IDD = 3 mA 5VREF 2 0.4 0.4 100 V V V V A IOL = 3 mA IOL = 3 mA VIL = VSS 0 0 IIL VGT Input current: PD1#, PD2#, EN/ TS Gate threshold 0.7 1.8 3.0 V 1. This value is set by the RD resistor. 2. See Table 8 for a listing of programmable under-voltage hysteresis settings. Summit Microelectronics 2050 3.7 10/30/02 15 AC Operating Characteristics - SMH4804 AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.) Symbol Description Conditions Min Typ Max Unit Comment tCBD = 5 s tCBD Programmable Over-Current Filter tCBD = 50 s1 tCBD = 150 s tCBD = 400 s tPGD = 50 s tPGD = 250 s tPGD = 500 s tPGD Programmable power good delay (PG1 PG2, PG2 PG3, PG3 PG4) tPGD = 1000 s tPGD = 5 ms1 -25 tPGD +25 -25 tCBD +25 s s s s % % % % % % % % 200 ns +25 % ns See Figure 7 See Figure 5 See Figure 6 See Figure 4 See Figure 5, Figure 6, Figure 7, and Figure 13 tPGD = 20 ms tPGD = 80 ms tPGD = 160 ms tQTSD tCYC tCBRST Quick-Trip shutdown Circuit breaker cycle mode cycle time CBRESET pulse width tPUVF = tPUVF Programmable under-voltage filter Off1 -25 tPUVF +25 tCYC = 2.5 s1 tCYC = 5 s -25 200 tCYC tPUVF = 5 ms tPUVF = 80 ms tPUVF = 160 ms tPDD = 0.5 ms % tPDD Programmable pin detect tPDD = 5 ms tPDD = 80 ms1 -25 tPDD +25 % See Figure 6 and Figure 13 tPDD = 160 ms 1. Indicates default value 16 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - I2C 2-Wire Serial Interface AC Operating Characteristics I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.) Symbol Parameter Conditions Min Max Units fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT tI tWR SCL clock frequency Clock period low Clock period high Bus free time1 Before new transmission Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data out hold time SCL and SDA rise time1 SCL and SDA fall Data in hold time Noise filter SCL and Write cycle time SDA1 Noise suppression time1 Data in setup time SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2 100 kHz s s s s s s 3.5 s s 1000 300 250 0 100 5 ns ns ns ns ns ms 1. Values are guaranteed by the design. - TIMING DIAGRAM Figure 12 shows a timing diagram for the Bus Interface Memory timing. The table above lists the AC timing parameters for Figure 12. One bit of data is transferred during each clock pulse. Note that data must remain stable when the clock is high. tR tF tHIGH tLOW SCL tSU:SDA tHD:DAT tSU:DAT tSU:STO tHD:SDA tBUF SDA In tAA tDH SDA Out 2050 Fig09 2.0 Figure 12. Bus Interface Memory Timing Summit Microelectronics 2050 3.7 10/30/02 17 Timing Diagram Power-on Timing SMH4804 Figure 13 illustrates some power on sequences, including the UV and OV differentials to their reference, and Power Good cascading. Refer to the table on page 17 for more information on the tPDD and tCBD timings. VDD 11 VDD 13 PD1#/ PD2# tPDD VDD - VGT VGATE VDD Note - A 'Fault' condition has caused Drain Sense to go high. 5V DRAIN SENSE 2.5VREF 50mVREF CBSENSE 2050 Fig01 2.1 Figure 13. SMH4804 Power-On Sequences 18 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Timing Diagram SMH4804 Power-On Waveforms - Ref to -48V Tektronix TDS3054: Time/Horizontal division = 40mS Ch 1 (2V/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 2 (50V/Div) = PG#2 output (Blue trace) - Note 1 Ch 3 (50V/Div) = Switched 48V supply voltage (Purple trace) Ch 4 (2A/Div) = Inrush input current (Green) Note 1 - After initial hot swap conditions are met, he PG# outputs first drop to -43V until ready to sequence the DC-DC converter. When ready to sequence, the PG# outputs then drop an additional 5V to enable the converters. SMH4804 Sequencing waveforms - Ref to GND Four DC/DC converters sequenced on at 160ms intervals 7HNWURQL[ 7'6 7LPH+RUL]RQWDO GLYLVLRQ Ch 1 (1V/Div) = 5.0V DC-DC converter output (Yellow trace) Ch 2 (1V/Div) = 3.3V DC-DC converter output (Yellow trace) Ch 3 (1V/Div) = 2.5V DC-DC converter output (Yellow trace) Ch 4 (1V/Div) = 1.8V DC-DC converter output (Yellow trace) P6 SMH4804 with 0.1uF and 0.01uF Soft-Start Capacitors Tektronix TDS3054: Time/Horizontal division = 40mS Ch 1 (50V/Div) = MOSFET Drain (Yellow trace) Ch 2 (5V/Div) = SMH4804 UV pin (Blue trace) Ch 3 (10V/Div) = MOSFET Gate (Purple trace) Ch 4 (2A/Div) = -48V Inrush input current (Green) SMH4804 with 1uF and 0.1uF Soft-Start Capacitors Tektronix TDS3054: Time/Horizontal division = 200mS Ch 1 (50V/Div) = MOSFET Drain (Yellow trace) Ch 2 (5V/Div) = SMH4804 UV pin (Blue trace) Ch 3 (10V/Div) = MOSFET Gate (Purple trace) Ch 4 (2A/Div) = -48V Inrush input current (Green) Summit Microelectronics 2050 3.7 10/30/02 19 Timing Diagram Operating at High Voltages The breakdown voltage of the external active and passive components limits the maximum operating voltage of the SMH4804 hot-swap controller. Components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in series with the DRAIN SENSE pin, the power MOSFET switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller's VDD pin. SMH4804 Next the minimum current that flows through the resistive divider, IDMIN, is calculated from the ratio of minimum and maximum supply voltage levels: IDMIN = Substituting: IDMAX x VSMIN VSMAX IDMIN = 250A x 36V = 125 2.5 V Over-Voltage and Under-Voltage Resistors In Figures 21, 22, and 23, the three resistors (R1, R2, and R3) connected to the OV and UV inputs must be capable of withstanding the maximum supply voltage of several hundred volts. The trip voltage of the UV and OV inputs is 2.5V relative to VSS. As the input impedance of UV and OV is very high, large value resistors can be used in the resistive divider. The divider resistors should be high stability, 1% metal-film resistors to keep the under-voltage and over-voltage trip points accurate. Now the value of R3 is calculated from IDMIN: R3 = VSMIN x VUV IDMIN VUV is the under-voltage trip point, also 2.5V. Substituting: R3 = 36V x 2.5V 125 = 286 k Telecom Design Example A hot-swap telecom application may use a 48V power supply with a -25% to +50% tolerance (i.e., the 48V supply can vary from 36V to 72V). The formula for calculating R1, R2, and R3 are as follows. First, a peak current, IDMAX, must be specified for the resistive network. The value of the current is arbitrary, but it cannot be too high (self-heating in R3 becomes a problem), or too low (the value of R3 becomes very large, and leakage currents can reduce the accuracy of the OV and UV trip points). The value of IDMAX should be 200A for the best accuracy at the OV and UV trip points. A value of 250A for IDMAX is used to illustrate the following calculations. With VOV (2.5V) being the over-voltage trip point, R1 is calculated by the formula: The closest standard 1% resistor value is 267 k Then R2 is calculated: VUV (R1 + R2) = ID MIN or VUV R2 = ID - R1 MIN Substituting: 2.5V R2 = 125 - 10 k = 20 k - 10 k = 10 k An Excel spread sheet is available on Summit's website (www.summitmicro.com) to simplify the resistor value calculations and tolerance analysis for R1, R2, and R3. R1 = VOV IDMAX Substituting: Dropper Resistor Selection 2.5V 250A = 10 K The SMH4804 is powered from the high-voltage supply via a dropper resistor, RD. The dropper resistor must provide the SMH4804 (and its loads) with sufficient operating current under minimum supply voltage conditions, but must R1 = 20 2050 3.7 10/30/02 Summit Microelectronics SMH4804 not allow the maximum supply current to be exceeded under maximum supply voltage conditions. The dropper resistor value is calculated from: Timing Diagram the worst case condition of 85C ambient. Using a 68 k resistor for RT gives: VDS(ON)THRESHOLD = 2.5V - (15A x 68k) - 0.5V = 1V RD = VSMIN - VDDMAX IDD - ILOAD where VSMIN is the lowest operating supply voltage, VDDMAX is the upper limit of the SMH4804 supply voltage, IDD is minimum current required for the SMH4804 to operate, and ILOAD is any additional load current from the 2.5V and 5V outputs and between VDD and VSS. Calculate the minimum wattage required for RD from: The voltage drop across the MOSFET switch and sense resistor, VDSS, is calculated from: VDSS = ID (RS x RON) where ID is the MOSFET drain current, RS is the circuit breaker sense resistor and RON is the MOSFET on resistance. The dropper resistor value should be chosen such that the minimum and maximum IDD and VDD specifications of the SMH4804 are maintained across the host supply's valid operating voltage range. First, subtract the minimum VDD of the SMH4804 from the low end of the voltage, and divide by the minimum IDD value. Using this value of resistance as RD find the operating current that would result from running at the high end of the supply voltage to verify that the resulting current is less than the maximum IDD current allowed. If some range of supply voltage is chosen that would cause the maximum IDD specification to be violated, then an external zener diode with a breakdown voltage of ~12V should be used across VDD. As an example of choosing the proper RD value, assume the host supply voltage ranges from 36 to 72V. The largest dropper resistor that can be used is: (36V-11V)/3mA = 8.3k. Next, confirm that this value of RD also works at the high end: (72V-13V)/8.3k = 7.08mA, which is less than 8mA. The FS# input can also be used in conjunction with a secondary-side supervisory circuit providing a positive feedback loop during the power up sequence. As an example, assume the SMH4804 is configured to turn on -48V to three DC/DC converters and then sequentially turn on the converters with a 1.6ms delay. Further assume all of the enable inputs are true and PG4# has just been sequenced on. If FS# option 4 (100BIN in register 5) has been selected, then FS# must be driven high within 1.6ms after PG4# goes low, otherwise all of the PG[4:1]# outputs are disabled. Ideally, there would be a secondary-side supervisor similar to the SMS44 that would have its reset time-out period programmed to be less than 1.6ms. After the last supply turns on the RESET# output of the SMS44 would be released and FS# pulled high. However, if for any reason 21 PR0 (VSMAX - VDDMIN)2 RD where VDDMIN is the lower limit of the SMH4804 supply voltage, and VSMAX is the highest operating supply voltage. In circumstances where the input voltage may swing over a wide range (e.g., from 20V to 100V) the maximum current may be exceeded. In these circumstances it may be necessary to add an 11V Zener diode between VDD and VSS to handle the wide current range. The Zener voltage should be below the nominal regulation voltage of the SMH4803A so that it becomes the primary regulator. MOSFET VDS(ON) Threshold The drain sense input on the SMH4804 monitors the voltage at the drain of the external power MOSFET switch with respect to VSS. When the MOSFET's VDS is below the userdefined threshold the MOSFET switch is considered to be ON. The VDS(ON)THRESHOLD is adjusted using the resistor, RT, in series with the drain sense protection diode. This protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the MOSFET switch is OFF. A low leakage MMBD1401 diode offers protection up to 100V. For high voltage applications (up to 500V) the Central Semiconductor CMR1F-10M diode should be used. The VDS(ON)THRESHOLD is calculated from: VDS(ON)THRESHOLD = VSENSE - (ISENSE x RT) - VDIODE where VDIODE is the forward voltage drop of the protection diode. The VDS(ON)THRESHOLD varies over temperature due to the temperature dependence of VDIODE and ISENSE. The calculation below gives the VDS(ON)THRESHOLD under Summit Microelectronics 2050 3.7 10/30/02 Timing Diagram not all of the supplies turn on, RESET# is not released and the SMH4804 disables the PG[4:1]# outputs. This termination timer function can be programmed to abort the sequence after PG1#, PG2#, PG3# or PG4#. SMH4804 secondary-side voltages. The SMH4804 Quad Hot Swap Controller is easily configured for independent on/off control of up to 4 individual DC-DC converters. A simplified schematic displaying the SMH4804 enable pins together with their respective output enabling pins is shown in Figure 14. The SMH4804 asserts each of its output enabling pins (PG[4:1]#) independently of one another as shown in Figure 14. Applying a logic high (3.5V - 5V) to any of the `ENABLE_PGx#' nodes forces the corresponding output to a logic low. For example, to turn on the first DC-DC converter (assuming its Enable pin requires a low to turn it on), `ENABLE_PG1#' must be high. Taking this node low forces the SMH4804 output to a high impedance (open-drain) state. Please refer to Application Brief AB-01 for more details. Soft Start Slew Rate Control The -48V turn on time is controlled by the SMH4804 and by the values of R4, C1 and C2 in Figures 21, 22, and 23. The turn on time is approximately 10ms with the component values shown in Figure 15. Increasing the capacitance reduces the output slew rate and increases the turn on time. The capacitors prevent the MOSFET from turning on simultaneously with the application of -48V. Resistor R4 is specified to limit the current into and the rate of charge of C1. The ratio of C1 to C2 (10:1) limits the MOSFET's VGS to approximately 5V once the -48V supply is connected and C1 is fully charged. Configuring the SMH4804 for Independent Control of DC-DC Converters for Power-onLAN IEEE 802.3 Certain systems employing live card insertion or `hotswapping' require independent control of the individual FS# PG1# ENPGA PG2# SMH4804 ENABLE PG1# To DC-DC #1 ENABLE PG1# To DC-DC #2 ENABLE PG1# To DC-DC #3 ENABLE PG1# To DC-DC #4 ENPGA PG3# ENPGA PG4# Figure 14. Configuring the SMH4804 as a Quad Independent Hot-Swap Controller. 22 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Timing Diagram -48V RTN (0V) 0V -48V RTN (0V) 0V RD 6.8k 1/2W 2.5VREF VDD ENPGA ENPGB ENPGC FS# 3 MMBTA06LT1 EN/TS R3 PG4# 100k UV PG3# R2 OV PD1# PD2# FAULT# RESET# MODE A0 A1 A2 SCL SDA VSS MMBTA06LT1 100k SMH4804 PG2# MMBTA06LT1 5VREF 100k 47k MMBTA06LT1 DRAIN SENSE CBSENSE PG1# MMBD1401 2 100nF 3.3nF R1 C1 100nF VGATE 50V R4 1k C2 10nF 100V RT 68k 4 100nF 50V 100F 100V 1 RG RS 20m 10 DD MMBD1401 -48V 2050 Fig16 -48V Figure 15. Changing Polarity of Power Good Output PG1# Notes: The 10 resistor (R ) must be located as close as possible to the MOSFET. Optional bypass capacitor. If a larger value is required an 11V zener must be connected in parallel. Optional interface circuit. The PG[4:1]# outputs can be directly connected to the power module if the input voltage to the module is within tolerance and the voltage on the PG[4:1]# outputs doesn't exceed 15V. The DRAIN Sense function may cause nuisance tripping due to voltage transients on the -48V line or when using multiple lines. This may be avoided by one of the following methods: A. Disable the function by connecting the DRAIN Sense pin to VSS directly. The components RT and DD are eliminated. B. Add a capacitor from DRAIN Sense to VSS. The exact capacitance value depends upon the magnitude and duration of the voltage transient appearing at the drain of the MOSFET. G Summit Microelectronics 2050 3.7 10/30/02 23 Timing Diagram SMH4804 -48V RTN (0V) 0V -48V RTN (0V) 0V R3 NTC 50k @TMAX RD 6.8k 1/2W 1k 100k 1M 2.5VREF VDD ENPGA ENPGB ENPGC - LMV331 50k EN/TS FS# + 3 MMBTA06LT1 PG4# 100k UV PG3# R2 OV PD1# PD2# FAULT# RESET# MODE A0 A1 A2 SCL SDA 5VREF PG1# 100k MMBTA06LT1 100k MMBTA06LT1 SMH4804 PG2# MMBTA06LT1 100k VSS DRAIN SENSE CBSENSE VGATE 2 100nF 3.3nF R1 C1 100nF R4 1k C2 10nF 100V 100nF 50V RT 68k 100F 100V 100nF 50V 50V 4 1 RG RS 20m 10 DD MMBD1401 -48V 2050 Fig17 -48V Figure 16. Over-temperature Shutdown Notes: The 10 resistor (RG) must be located as close as possible to the MOSFET. Optional bypass capacitor. If a larger value is required an 11V Zener must be connected in parallel. Optional interface circuit. The PG[4:1]# outputs can be directly connected to the power module if the input voltage to the module is within tolerance and the voltage on the PG[4:1]# outputs doesn't exceed 15V. The DRAIN Sense function may cause nuisance tripping due to voltage transients on the -48V line or when using multiple lines. This may be avoided by one of the following methods: A. Disable the function by connecting the DRAIN Sense pin to VSS directly. The components RT and DD are eliminated. B. Add a capacitor from Drain Sense to VSS. The exact capacitance value depends upon the magnitude and duration of the voltage transient appearing at the drain of the MOSFET. 24 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Timing Diagram -48V RTN (0V) 0V R3 RD 6.8k 1/2W 100k VDD ENPGA ENPGB ENPGC EN/TS FS# 3 PG4# MMBTA06LT1 +VIN +VOUT -VIN -VOUT ON/OFF V4 0V 100k UV PG3# R2 MMBTA06LT1 +VIN +VOUT -VIN -VOUT ON/OFF V3 ISOLATED DC OUTPUTS SMH4804 OV PD1# PD2# DRAIN SENSE CBSENSE 100k PG2# MMBTA06LT1 +VIN +VOUT -VIN -VOUT ON/OFF V2 VGATE FAULT# RESET# MODE VSS 5VREF PG1# 100k MMBTA06LT1 +VIN +VOUT -VIN -VOUT ON/OFF DC / DC Converters with Active Low On/Off Control V1 100k R1 C1 100nF R4 1k C2 10nF 100V RT 4 68k DD MMBD1401 100nF 50V 100F 100V 2 100nF 3.3nF 50V RS 1 RG 10 -48V 2050 Fig18 Figure 17. Typical Application Sequencing Four DC/DC Converter Notes: The 10 resistor (RG) must be located as close as possible to the MOSFET. Optional bypass capacitor. If a larger value is required an 11V Zener must be connected in parallel. Optional interface circuit. The PG[4:1]# outputs can be directly connected to the power module if the input voltage to the module is within tolerance and the voltage on the PG[4:1]# outputs doesn't exceed 15V. The DRAIN Sense function may cause nuisance tripping due to voltage transients on the -48V line or when using multiple lines. This may be avoided by one of the following methods: A. Disable the function by connecting the DRAIN Sense pin to VSS directly. The components RT and DD are eliminated. B. Add a capacitor from DRAIN Sense to VSS. The exact capacitance value depends upon the magnitude and duration of the voltage transient appearing at the drain of the MOSFET. Summit Microelectronics 2050 3.7 10/30/02 25 Timing Diagram SMH4804 IRQ# -48V RTN (0V) 0V SMS44 RD VDD FS# 5VREF PGx# VSS DRAIN SENSE SMH4804 CBSENSE VGATE I n t e r f a c e + DC/DC - 2050 Fig19 -48V Figure 18. Controlling FS# with Secondary Feedback CHASSIS CARD -48V RTNRet -48V (0V) VDD PD1# 9 6KRUW 3LQV 9 3' 3' SMH4804 -48V A PD2# 9 VSS -48V B Short Pins 2050 Fig20 Figure 19. PD1# and PD2# Inputs, Physical Offset 26 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - Programming Information PROGRAMMING INFORMATION I2CBus Interface The I2C bus is a two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA) and a serial clock line (SCL). The SMH4804 supports a 100 kHz clock rate. The SDA line must be connected to a positive supply by a pull-up resistor located on the bus. The SMH4804 contains a Schmitt input on both the SDA and SCL signals. Start and Stop Conditions Both the SDA and SCL pins remain high when the bus is not busy. Data transfers between devices may be initiated with a Start condition only when SCL and SDA are high. A highto-low transition of the SDA while the SCL pin is high is defined as a Start condition. A low-to-high transition SDA while SCL is high is defined as a Stop condition. Figure 20 shows a timing diagram of the start and stop conditions. When the last byte has been transferred to the Master during a read of the SMH4804, the Master leaves SDA high for a Not Acknowledge (NACK) cycle. This causes the SMH4804 part to stop sending data, and the Master issues a Stop on the clock pulse following the NACK. Figure 21 shows the Acknowledge timing. SCL 1 2 3 8 9 SDA Trans SDA Rec ACK 2050 Fig11 Figure 21. Acknowledge Timing Read and Write The first byte from a Master is always made up of a 7-bit Slave address and the Read/Write (R/W) bit. The R/W bit tells the Slave whether the Master is reading data from the bus or writing data to the bus (1 = Read, 0 = Write). The first four of the seven address bits are called the Device Type Identifier (DTI). The DTI for the SMH4804 is 1010BIN. The next three bits are Address values for A2, A1, and A0 (if multiple devices are used). The SMH4804 issues an Acknowledge after recognizing a Start condition and its DTI. Figure 22 shows an example of a typical master address byte transmission. SCL 1 2 3 4 5 6 7 8 9 START Condition SCL STOP Condition SDA In 2050 Fig10 2.0 Figure 20. Start and Stop Conditions Master/Slave Protocol The master/slave protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. The device controlling data transmission is called the Master, and the controlled device is called the Slave. In all cases the SMH4804 is referred to as a Slave device since it never initiates any data transfers. Acknowledge Data is always transferred in bytes. Acknowledge (ACK) is used to indicate a successful data transfer. The transmitting device releases the bus after transmitting eight bits. During the ninth clock cycle the Receiver pulls the SDA line low to acknowledge that it received the eight bits of data. This is shown by the ACK callout in Figure 21. SDA 1 0 1 0 x x x R/W ACK 2050 Fig12 Figure 22. Typical Master Address Byte Transmission During a read by the Master device, the SMH4804 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no Stop condition is generated by the Master, the SMH4804 continues to transmit data. If an Acknowledge is not detected (NACK), the SMH4804 terminates any subsequent data transmission. The read transfer protocol on SDA is shown in Figure 23. Summit Microelectronics 2050 3.7 10/30/02 27 Programming Information SMH4804 followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4804 to the desired address. Master SDA Slave S T A R T R / W 1010xxxRxxx xxxxx A C K A C K xx xx N A C K S T O P 2050 Fig13 Figure 23. Read Protocol During a Master write, the SMH4804 receives eight bits of data, then generates an Acknowledge signal. It device continues to generate the ACK condition on SDA until a Stop condition is generated by the Master. The write transfer protocol on SDA is shown in Figure 24. After the word address Acknowledge is received by the Master, it immediately reissues a Start condition followed by another Slave address field with the R/W bit set to Read. The SMH4804 responds with an Acknowledge and then transmits the 8 data bits stored at the addressed location. At this point, the Master sets the SDA line to NACK and generates a Stop condition. The SMH4804 discontinues data transmission and reverts to its standby power mode. Sequential Reads Master SDA Slave S T A R T R / W 1 0 1 0 x x xW A C K xxxxxxxx A C K xx xx A C K S T O P Sequential reads can be initiated as either a current address read or a random access read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read). However, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4804. The SMH4804 continues to output data for each Acknowledge received. The Master sets the SDA line to NACK and generates a Stop condition. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter rolls over and the memory continues to output data. 2050 Fig14 Figure 24. Write Protocol Random Access Read Random address read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condition and the Slave address field (with the R/W bit set to Write) Master SDA Slave S T A R T DEVICE IDENTIFIER Typical Write Operation S T O P DDDDDDDD 76543210 10 AA A R 1 1 21 0 / W BUS ADDRESS AA A A A A A A 76 5 4 3 2 1 0 A C K A C K A C K S T A R T 10 AA A R 1 1 21 0 / W A C K DDDDDDDD 76543210 Master SDA Slave S T A R T DEVICE IDENTIFIER Typical Read Operation N A C K S T O P 10 AA A R 1 1 21 0 / W BUS ADDRESS AA A A A A A A 76 5 4 3 2 1 0 A C K A C K 2050 Fig15 3.0 Figure 25. Sequential Bus Cycles 28 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Register Access The SMH4804 contains a 2-wire bus interface for register access as explained in the previous section. This bus is highly configurable, while maintaining the industry standard protocol. The SMH4804 responds to one of two selectable Device Type Addresses: 1010BIN, generally assigned to NVmemories, or 1011BIN, which is the default address for the SMH4804. The Device Type Address is assigned by programming bit 3 of Register 8. Register accesses are also programmable using bits 2:1 of Register 8. Accesses can be denied (no reads or writes), read only, or read/write (default state). The SMH4804 has three address pins, A[2:0], associated with the 2-wire bus. The SMH4804 can be configured to respond to: * only to the proper serial data string of the Device Type Address and specific bus addresses (Register 8, bit 0 set). * the Device Type Address and any bus address (Register 8, bit 0 cleared). -48V Programming Information Top view of straight 0.1" x 0.1" closed side connector SMX3200 interface Pin 10, Reserved Pin 8, Reserved Pin 6, Reserved Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin5, Reserved Pin3, GND Pin 1, GND -48V RTN (0V) 0V RD VDD A0 A1 SMH4804 A2 SDA VSS SCL 10 8 6 4 2 9 7 5 3 1 C1 0.01F 2050 Fig08 Figure 26. SMH4804 Programming Connection Caution: Damage may occur when connecting the dongle to a system utilizing an earth-connected positive terminal. Master/Slave Protocol The master/slave protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. The SMH4804 is always a Slave device, since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because a change on the data line while SCL is high is interpreted as either a Start or a Stop condition. Development Hardware and Software The end user can use the Summit SMX3200 programming cable and software to connect the board containing the SMH4804 to the personal computer. See Figure 26 for board connections. The programming cable interfaces directly between a PC's parallel port and the and the 10-pin connector shown in Figure 26. The application's values are entered via an intuitive graphical user interface employing drop-down menus. After the desired settings for the application are determined the software generates a hex file that can be written to the SMH4804. This file contains the customer part number and is used to customize the devices during the final electrical test operations. Figure 26 shows a diagram of the SMH4804 programming connections. Register Bit Maps The SMH4804 has eight user programmable, nonvolatile, configuration registers. Although 8-bit data transfers are used for reading and writing the registers, only the 4 lease significant bits of each register are utilized by the device. Therefore, in each of the following registers, bits 7:4 are left blank. Bits 3:0 are used as shown for each register. Summit Microelectronics 2050 3.7 10/30/02 29 Default Configuration Register Settings -- SMH4804F-019 - SMH4804 DEFAULT CONFIGURATION REGISTER SETTINGS -- SMH4804F-019 Register Hex Contents Description R02 R03 R04 R05 R06 R07 R08 R09 R0C 9 2 8 C C 9 1 9 0 Over-current delay and Quick-Trip over-current reference level. Power-good sequencing delay, CB mode enable, and PD[2:1]# pin-detect enable. PG[4:1]# Power-good sequence enable, over/under voltage filter delay, circuit breaker cycle time. Non-volatile fault latch enable, FS# forced shutdown function control. Under-voltage filter enable, over-voltage filter enable, VGATE current regulation control. Under-voltage hysteresis control. I2C control, including device type address, configuration register R/W status, and slave address response control. Power-good sequence speed, PD[2:1]# pin detect delay time. Non-volatile fault latch. Set by hardware when a fault is detected. Table 2. SMH4804 Default Register Settings 30 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - Registers REGISTERS Register 2 - Address 0010 This register is used to select both the over-current delay and the quick trip threshold for the electronic circuit breaker. Bits 3 2 1 0 Default R/W Description 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0b01 0b10 R/W R/W R/W R/W R/W R/W R/W R/W Set Over-current delay to 400 s. Set Over-current delay to 150 s. Set Over-current delay to 50 s. Set Over-current delay to 5 s. Set Quick Trip reference voltage to 200 mV. Set Quick Trip reference voltage to 100 mV. Set Quick Trip reference voltage to 60 mV. Set Quick Trip reference voltage off. Table 3. Register 2 Bitmap Summit Microelectronics 2050 3.7 10/30/02 31 Registers Register 3 - Address 0011 SMH4804 This register is used to control the sequencing delays from PG1# to PG2#, PG2# to PG3#, and PG3# to PG4#. The SMH4804 provides two levels of sequencing delay: fast and slow, which is selected by programming bit 3 of Register 9. These two bits are effectively concatenated with R9 bit 3, providing 8 programmable delay periods. Refer to Register 9 for more information. NOTE - Bit 1 controls the effect of the MODE pin. When set (high) the pin functions as described in the pin descriptions. If the bit is cleared (low) the state of the pin is ignored and the circuit breaker enters latch mode. Bit 0 enables or disables the function of the PD[4:1]# inputs Bits 3 2 1 0 Default R/W Description Register 9, bit 3 = 0 0 0 1 1 0 1 0 1 0b00 R/W PG[4:1]# Sequencing delay: 1500 s. PG[4:1]# Sequencing delay: 50 s. PG[4:1]# Sequencing delay: 250 s. PG[4:1]# Sequencing delay: 500 s. Register 9, bit 3 = 1 0 0 1 1 0 1 0 1 0b00 R/W PG[4:1]# Sequencing delay: 5 ms. PG[4:1]# Sequencing delay: 20 ms. PG[4:1]# Sequencing delay: 80 ms. PG[4:1]# Sequencing delay: 160 ms. Register 9, bit 3 = 1 or 0 0 1 0 0b0 1 0b1 R/W When bit 1 is cleared (0), the CB MODE MODE is disabled (see NOTE above). When bit 1 is set (1), the CB MODE is enabled (see NOTE above). When bit 0 is cleared, the PD1# and PD2# signals are disabled. When bit 0 is set, the PD1# and PD2# signals are enabled. Table 4. Register 3 Bitmap 32 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Register 4 - Address 0100 Registers Register 4 enables PG[4:1]# signal sequencing, sets the O/U voltage filter timing, and selects the circuit breaker cycle time. Bit 3 of this register enables or disables the PG[4:1]# sequence delays. When set, the delays are defined in registers 3 and 9. If bit 3 is cleared, no delay is incurred and sequencing is based solely on the state of the ENPGA#, ENPGB#, and ENPGC# inputs. If the ENPGx# inputs are tied high, the PG[4:1]# outputs turn on simultaneously. Bits 3 2 1 0 Default R/W Description 0 0b1 1 0 0 1 1 0 1 0 1 0 1 0b00 R/W R/W When bit 3 is cleared, PG[4:1]# signal sequencing is simultaneous. When bit 3 is set, PG[4:1]# signal sequencing is enabled. When bits 2:1 are set to 0b00, the over/under voltage filter is off. When bits 2:1 are set to 0b01, the over/under voltage delay is 5 ms. When bits 2:1 are set to 0b10, the over/under voltage delay is 80 ms. When bits 2:1 are set to 0b11, the over/under voltage delay is 160 ms. 0b0 R/W When bit 0 is cleared, the circuit breaker cycle time is 2.5 sec. When bit 0 is set, the circuit breaker cycle time is 5 sec. Table 5. Register 4 Bitmap Summit Microelectronics 2050 3.7 10/30/02 33 Registers Register 5 - Address 0101 SMH4804 Register 5 controls the function of the nonvolatile fault latch and provides general control for the FS# input. Bit 3 controls the enabling of the non-volatile latch. Bits 2:0 configure the FS# input. The FS# pin has two basic functions: it can be programmed to act as an auxiliary enable input controlling the PG1# output, or it can be programmed to be an event monitor during the power-up sequence. These bits also control the interrelationship of the PG[4:1]# outputs. In a cascade operating mode PG1# must be true before PG2# can be true, etc. This interrelationship can be disabled so that each PG[4:1]# output is effectively controlled by its corresponding ENGPx# input, as long as the primary supply, VGATE and DRAIN SENSE pins are within their operating limits. When programmed as an enable to PG1# there are two options: 010BIN disables the cascade mode (the PG[4:1]# outputs can act independently) and FS# effectively becomes the enable input for PG1#; 011BIN enables the cascade mode and makes FS# the enable input for PG1#. In this mode, PG1# must be active before PG2# can be activated, followed by PG3#, then PG4#. The event monitor mode is generally implemented in conjunction with a monitoring device on the secondary side of the DC/DC converters, such as the SMS44, SMT4004 or SMS64. If FS# is not pulled high before the programmed condition then the PG[4:1]# and VGATE outputs are shut down. As an example, if the binary value is 111BIN, VGATE and PG1# are shut down if FS# is not pulled high before tPGD has elapsed after PG1# is true. None of the other PG[4:1]# outputs are activated. If a failure occurs due to the lapse of the event monitor timer, cycling the power resets the device. Bits 3 2 1 0 Default R/W Description 0 1 0 0 0 0 0 1 0 1 0 0b1 R/W When bit 3 is cleared, the non-volatile latch is enabled. When bit 3 is set, the non-volatile latch is disabled. When bits 2:0 are 0b000, the FS function: PG4 + tPGD cascade is disabled for simultaneous assertion of the PG[4:1]# pins. When bits 2:0 are 0b001, the FS function is disabled (=1). When bits 2:0 are 0b010, the FS function is active (=1) before PG1 enabled. Cascade disabled for simultaneous assertion of the PG[4:1]# pins. 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0b100 R/W When bits 2:0 are 0b011, the FS function must be high (deasserted) before PG1 is enabled. FS function: PG4 + tPGD (PG Delay) FS function: PG3 + tPGD (PG Delay) FS function: PG2 + tPGD (PG Delay) FS function: PG1 + tPGD (PG Delay) Table 6. Register 5 Bitmap 34 2050 3.7 10/30/02 Summit Microelectronics SMH4804 Registers One last event mode, 000BIN, disables the cascade effect and sets up PG4# going true as the trigger event. FS# must be pulled high before tPGD elapses, or VGATE and all of the PG[4:1]# outputs are disabled. Cascade enabled: ENPGA enables PG2#, PG3# and PG4#; ENPGB enables PG3# and PG4#; ENPGC enables PG4#. Cascade disabled: ENPGA enables PG2#; ENPGB enables PG3#; ENPGC enables PG4#. Simultaneous: PG1#, PG2#, PG3# and PG4# operate independently from one another. Sequenced: PG1#, PG2#, PG3# and PG4# are dependent upon activation of PG(N-1) -- for N = 2, 3, and 4 -- plus a programmable PG delay.p=On Summit Microelectronics 2050 3.7 10/30/02 35 Registers Register 6 - Address 0110 SMH4804 This register enables what events are recorded in the nonvolatile fault latch if bit 3 of R5 is cleared. The high order bits of this register control whether the under and over voltage pins are filtered, and the two low order bits program the current regulation time period. Bits 3 2 1 0 Default R/W Description 0 1 0 1 0 0 1 1 0 1 0 1 0b1 R/W When bit 3 is cleared, the under voltage is filtered. When bit 3 is set, the under voltage is not filtered. When bit 2 is cleared, the over voltage is filtered. When bit 2 is set, the over voltage is not filtered. When bits 1:0 are set to 0b00, the current regulation is turned off. 0b1 R/W 0b00 R/W When bits 1:0 are set to 0b01, the current regulation is 5 ms. When bits 1:0 are set to 0b10, the current regulation is 80 ms. When bits 1:0 are set to 0b11, the current regulation is 160 ms. Table 7. Register 6 Bitmap Register 7 - Address 0111 This register controls the UV hysteresis. The values shown are with respect to VSS. Bits 3 2 1 0 Default R/W Description 1 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 1 0b1 R/W In this register, bit 3 is always set. When bits 2:0 are 0b000, the UV hysteresis = 0.0 volts. When bits 2:0 are 0b001, the UV hysteresis = 0.0625 volts. When bits 2:0 are 0b010, the UV hysteresis = 0.125 volts. 0b001 R/W When bits 2:0 are 0b011, the UV hysteresis = 0.1785 volts. When bits 2:0 are 0b100, the UV hysteresis = 0.250 volts. When bits 2:0 are 0b101, the UV hysteresis = 0.3125 volts. When bits 2:0 are 0b110, the UV hysteresis = 0.375 volts. When bits 2:0 are 0b111, the UV hysteresis = 0.4375 volts. Table 8. Register 7 Bitmap 36 2050 3.7 10/30/02 Summit Microelectronics Register 8 - Address 1000 This register is used to control the I2C bus interface activity. Bit 3 determines the Device Type Address, bits 2 and 1 select the register access capability, and bit 0 determines whether the device must receive a bus address that corresponds to the biasing of the address pins. Note: If the fault latch option is selected and write access is denied the SMH4804 cannot be cleared of a fault condition. Bits 3 2 1 0 Default R/W Description 0 1 0 0 1 1 0 1 0 1 0 1 0b0 R/W When bit 3 is cleared, the device type address is 1011. When bit 3 is set, the device type address is 1010. When bits 2:1 are set to 0b00, the Configuration registers are read/write (R/W). 0b00 R/W When bits 2:1 are set to 0b01, the Configuration registers are read-only (RO). When bits 2:1 are set to 0b10 or 0b11, I2C access to the Configuration registers is disabled. When bit 0 is cleared, the SMH4804 responds to all address pins. When bit 0 is set, the SMH4804 responds to the address set by the address pin pin polarities (A0,A1 and A2). Table 9. Register 8 Bitmap 0b1 R/W 37 Summit Microelectronics Registers Register 9 - Address 1001 SMH4804 In this register, bit 3 works in conjunction with Register 3, bits 2 and 3. Refer to the Register 3 description for details. Bit 2 sets UV/OV conditions to be either latched or not latched. Bits 1 and 0 select the delay from the point where both PD[2:1]# inputs are low (or initial power up conditions) to when sequencing can commence. Bits 3 2 1 0 Default R/W Description 0 1 0 0b1 R/W When bit 3 is cleared, the power good sequence is set to Fast. When bit 3 is set, the power good sequence is set to Slow. When bit 2 is cleared, UV/OV conditions are not latched. When bit 2 is set, UV/OV conditions are latched. When bits 1:0 are set to 0b00, the PD delay is 0.5 ms. 0 1 0 0 1 1 0 1 0 1 0b0 R/W 0b01 R/W When bits 1:0 are set to 0b01, the PD delay is 80 ms. When bits 1:0 are set to 0b10, the PD delay is 160 ms. When bits 1:0 are set to 0b11, the PD delay is 320 ms. Table 10. Register 9 Bitmap Register C - Address 1100 This register is not a configuration register, but rather a nonvolatile fault latch (NVFL). If a circuit breaker fault condition is detected and the NVFL is enabled (Register 5, Bit 3 cleared), bit 0 of Register C is automatically set (written with a logic `1') when the circuit breaker trips. So long as the bit remains set, the SMH4804 is not able to drive VGATE or the PG[4:1]# outputs. The host or service center must access the register and clear the bit (write a `0') once the fault condition has been resolved. The bit can also be used as a nonvolatile Power on/off control to power the SMH4804 and system through the I2C bus. Bits 3 2 1 0 Default R/W Description 0 When bit 0 is cleared, the NV fault latch is cleared. This bit is cleared by software once the fault condition is resolved. 1 0b0 R/W outputs will power the system on. When cleared by an I2C command, the VGATE and PG[4:1]# When bit 0 is set, the NV fault latch is set. This bit is set automatically by hardware when a fault is detected. outputs will power the system off. Table 11. Register 9 Bitmap When set by an I2C command, the VGATE and PG[4:1]# 38 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - Packaging PACKAGING Figure 27 shows the package dimensions for the 28-pin SOIC package. 0.701 - 0.711* (17.01 - 18.06) Ref Jedec MS-013 0.394 - 0.419 (10.00 - 10.65) 0.291 - 0.299 (7.391 - 7.595) 0.010 - 0.029 (0.254 - 0.737) o x45 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143 o o 0 to 8 typ MAX 0.050 (1.270) 0.014 - 0.019 (0.356 - 0.482) 0.004 - 0.012 (0.102 - 0.305) 0.009 - 0.013 (0.229 - 0.330) 0.016 - 0.050 (0.406 - 1.270) Figure 27. 28-Pin SOIC Package Summit Microelectronics 2050 3.7 10/30/02 39 Packaging Figure 28 shows the package dimensions for the 48-pin TQFP package. SMH4804 0.354 (9.00) 0.276 (7.00) B SC (A) Inches (M illimeters) B SC (B ) 0.02 (0.5) B SC 0.007 - 0.011 (0.17 - 0.27) (B ) (A) D ET AIL "A" R ef Jedec M S-026 0.037 - 0.041 0.95 - 1.05 0.039 (1.00) Pin 1 Ind icato r Ref 0.047 M AX. (1.2) 0 o to 7 o M AX 0 o M in to 7 o M ax A B 0.002 - 0.006 (0.05-0.15) 0.018 - 0.030 (0.45 - 0.75) D ETAIL "B " Figure 28. 48-Pin TQFP Package 40 2050 3.7 10/30/02 Summit Microelectronics SMH4804 - Ordering Information ORDERING INFORMATION SMH4804 Base Part Number F nnn Part Number Suffix Package F = TQFP S = SOIC - PART MARKING NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 3.7 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates. (c) Copyright 2002 SUMMIT MICROELECTRONICS, Inc. I2C is a trademark of Philips Corporation. Power Management for CommunicationsTM Summit Microelectronics 2050 3.7 10/30/02 41 |
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